1. Technical Field
The present disclosure relates to processes for manufacturing a semiconductor package, and, more particularly, to an electronic package, a semiconductor substrate of the electronic package and a method for manufacturing an electronic package that has an increased production yield.
2. Description of Related Art
With the rapid development of the electronics industry, electronic products are manufactured following a multi-purpose, high-performance trend. Techniques currently used in the field of chip packaging includes flip-chip packages, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (MCM), or chip stacking technique that integrates chips into a three-dimensional stack of chips (3D IC).
FIG. 1 is a cross-sectional diagram of a traditional semiconductor package 1. The semiconductor package 1 includes a package substrate 11 and a semiconductor chip 10, with a through silicon interposer (TSI) 13 disposed therebetween. The TSI 13 has through-silicon vias (TSVs) 130 and a redistribution layer (RDL) 131 formed on the top of the TSVs 130, such that the TSVs 130 are electrically connected to solder pads 110 of the package substrate 11 with a greater pitch by a plurality of conductive elements 16. Conductive elements 16 are then covered with underfill 15. Electrode pads 100 of the semiconductor chip 10 with a smaller pitch are electrically connected to the RDL 131 by a plurality of solder bumps 101. The solder bumps 101 are then covered by underfill 14. Finally, an encapsulant 12 is formed on the package substrate 1 to encapsulate the semiconductor chip 10 and the TSI 13.
In a subsequent manufacturing process, a plurality of solder balls 17 are disposed on the lower side of the package substrate 11 for a circuit board (not shown) to be combined therewith.
However, in the manufacturing processes of the traditional semiconductor package 1, before a singulation process is performed, the whole structure 1′ (including a plurality of semiconductor packages 1) as shown in FIG. 1′, when experiencing a high-temperature operation such as a reflow process, may undergo warpage as a result of large mismatch between the coefficients of thermal expansion (CTE) of the semiconductor chip 10, the encapsulant 12 and the TSI 13. Warpage may be convex bending (such as that shown in FIG. 1′) or concave bending. As a result, the semiconductor package 1 after the singulation process is performed will not stay flat, and issues such as non-wetting may occur when the semiconductor package 1 is subsequently attached to the circuit board, causing poor electrical connection.
Therefore, there is a need for a solution that addresses the aforementioned issues in the prior art.